PPC5605BEMLLR datasheet(67/92 Pages) FREESCALE

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Electrical characteristics

MPC5607B Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

9tSUO

Data valid

after SCK

edge

Master

(MTFE =

—

Slave

—

Master

(MTFE =

——

tHO

Data hold

time for

outputs

Master

(MTFE =

2—

—

Slave

5.5

—

Master

(MTFE =

2—

—

1 Maximum is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM pad.

2 The t

CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields

in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than

Δt

CSC to ensure

positive tCSCext.

3 The t

ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in

DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than

Δt

ASC to ensure positive

tASCext.

4 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.

5 SCK and SOUT configured as MEDIUM pad

Table 41. DSPI characteristics (continued)

No.

Symbol

Parameter

Value

Unit

Min

Typ

Max

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