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AS1716

Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s

10 Package Drawings and Markings

The device is available in a 8-pin SOIC package.

Figure 14. 8-pin SOIC Package Dimensions

Symbol

Min

Max

A1.52

1.72

A1

0.10

0.25

A2

1.37

1.57

B0.36

0.46

C0.19

0.25

D4.80

4.98

E3.81

3.99

e1.27BSC

H5.80

6.20

h0.25

0.50

L0.41

1.27

α

0º

8º

ZD

0.53REF

Notes:

1. Lead coplanarity should be 0 to 0.10mm (.004”) max.

2. Package surface finishing:

- Top, matte (charmilles #18-30)

- All sides, matte (charmilles +18-30)

- Bottom, smooth or matte (charmilles +18-30)

3. All dimensions excluding mold flashes and end flash from the pack-

age body shall not exceed 0.25mm (.010”) per side.

4. Details of pin #1 mark are optional but must be located within the

area indicated.