DM562AP datasheet(22/48 Pages) DAVICOM

22 / 48 page

DM562AP

V.90 Integrated Data/ Fax/Voice/Speakerphone

Modem Device Single Chip with Memory Built in

Final

Version: DM562AP-DS-F03

10. Micro-controller Control Register for PCI

interface

PCI Vender ID Low Byte Data Port: Address

F800H (pci only)

Write only

This port configures PCI Vender ID low byte. (Offset

00 of PCI configuration register space)

PCI Vender ID High Byte Data Port: Address

F801H (pci only)

Write only

This port configures PCI Vender ID high byte.

(Offset 01 of PCI configuration register space)

PCI Device ID Low Byte Data Port: Address F802H

Write only

This port configures PCI Device ID low byte.

(Offset

02 of PCI configuration register space)

PCI Device ID High Byte Data Port: Address

F803H

Write only

This port configures PCI Device ID low byte.( Offset

00 of PCI configuration register space)

PCI Subsystem Vender ID Low Byte Data Port:

Address F804H (pci only)

Write only

This port configures PCI Subsystem Vender ID low

byte. (Offset 2C of PCI configuration register space)

PCI Subsystem Vender ID High Byte Data Port:

Address F805H (pci only)

Write only

This port configures PCI Subsystem Vender ID high

byte. (Offset 2D of PCI configuration register space)

PCI Subsystem Device ID Low Byte Data Port:

Address F806H

Write only

This port configures PCI Subsystem Device ID low

byte.

(Offset 2E of PCI configuration register space)

PCI Subsystem Device ID High Byte Data Port:

Address F807H

Write only

This port configures PCI Subsystem Device ID low

byte.

(Offset 2F of PCI configuration register space)

PCI Power Management New Capability: Address

F808H, Bit 4 (pci only)

Write only

This bit configures if support PCI Power Management.

(Offset 06 bit 4 of PCI configuration register space)

PCI Power Management Power State:

Address F809H, Bit[1..0] (pci only)

Write / Read

These bits configure PCI Power management Power

State.

(Offset 54 bit [1..0] of PCI configuration

PCI Power Management PME_STATUS:

Address F80AH, Bit 1

Write only

This bit configures PCI Power status.

(Offset 55 bit

7 of PCI configuration register space)

PCI Power Management PME_EN:

Address F80AH, Bit 0

Write only

This bit configures PCI if enable PME wake up

(Offset 55 bit 0 of PCI configuration register space)

PCI PME_D3_Support:

Address F80BH, Bit 0

Write only

This port configures PCI if support PME wake up at

D3 state. (Offset 53 bit [8..7] of PCI configuration

Nov. 09, 2007

DM562AP Datasheet(PDF) 22 Page - Davicom Semiconductor, Inc.

DM562AP Datasheet(HTML) 22 Page - Davicom Semiconductor, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Descarga

Enlace URL