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MPC5123 Datasheet(PDF) 66 Page - Freescale Semiconductor, Inc |
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MPC5123 Datasheet(HTML) 66 Page - Freescale Semiconductor, Inc |
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66 / 86 page ![]() MPC5121E/MPC5123 Data Sheet, Rev. 4 Electrical and Thermal Characteristics Freescale Semiconductor 66 Figure 46. Timing Diagram – 8, 16, 24, and 32-bit CODEC/I2S Master Mode NOTE Output timing is specified at a nominal 50 pF load. Table 42. Timing Specifications – 8, 16, 24, and 32-bit CODEC/I2S Slave Mode Sym Description Min Typ Max Units SpecID 1 Bit Clock cycle time 40.0 — — ns A20.9 2 Clock duty cycle — 50 — %1 1 Bit Clock cycle time A20.10 3 FrameSync setup time 1.0 — — ns A20.11 4 Output Data valid after clock edge — — 14.0 ns A20.12 5 Input Data setup time 1.0 — — ns A20.13 6 Input Data hold time 1.0 — — ns A20.14 BitClk Output 5 3 4 3 4 (CLKPOL=0) BitClk Output (CLKPOL=1) FrameSync Output (SyncPol = 1) TxD Output 6 7 8 FrameSync Output (SyncPol = 0) RxD Input 1 2 2 |
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