ADP5022ACBZ-2-R7 datasheet(22/28 Pages) AD

No. de pieza	ADP5022ACBZ-2-R7

Descripción Electrónicos	Dual 3 MHz, 600 mA Buck Regulator with 150 mA LDO

PDF	28 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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22 / 28 page

ADP5022

Rev. A | Page 22 of 28

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5022 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to

the component side ground to further reduce noise

interference on sensitive circuit nodes.

ADP5022ACBZ-2-R7 Datasheet(PDF) 22 Page - Analog Devices