ATtiny5 datasheet(55/168 Pages) ATMEL

55 / 168 page

8127C–AVR–10/09

ATtiny4/5/9/10

clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 sys-

tem clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program

execution.

11.3.2

External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkTn). The

Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 11-3 on page 55 shows

a functional equivalent block diagram of the T0 synchronization and edge detector logic. The

registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is trans-

parent in the high period of the internal system clock.

The edge detector generates one clkT0 pulse for each positive (CS2:0 = 7) or negative (CS2:0 =

6) edge it detects.

Figure 11-3. T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.

An external clock source can not be prescaled.

11.4 Counter Unit

The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.

Figure 11-4 on page 56 shows a block diagram of the counter and its surroundings.

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

ATtiny5 Datasheet(PDF) 55 Page - ATMEL Corporation