AT697F datasheet(75/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Figure 49.

SKEW[1:0]

CLK1 tree

CLK2 tree

CLK3 tree

BYPASS

CLK

PLL

cpu clock

D2 = D1

D4 = D3 = 2 * D1

CPU clock tree overview

Three configuration of skew are available :

•

SKEW[1:0] = ’00’ : natural skew corresponding to the intrinsec routage of the chip

•

SKEW[1:0] = ’01’ : medium skew ‘artificially’ injected

•

SKEW[1:0] = ’10’ : maximum skew ‘artificially’ injected

The remaining configuration (SKEW[1:0] = ’11’) is reserved and must not be used at application

level.

Table 28. SKEW assignements

SKEW[1:0]

DELAY

Comments

CLK1 -> CLK2

CLK1 -> CLK3

‘00’

natural

natural skew

‘01’

medium skew

‘10’

D1 + D2

D3 + D4

maximum skew

‘11’

Reserved

Use of a high level of skew improves the efficiency of SET prevention but leads to an operating

loss performance. Maximum speed is decreased and timings on the interfaces are slower than

with natural skew. Refer to the ’Electrical Characteristics’ section for detailed timings at each

skew.

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