AT89LP428 datasheet(97/149 Pages) ATMEL

97 / 149 page

3654A–MICRO–8/09

AT89LP428/828

17.5

SPI Registers

Notes:1. Set up the clock mode before enabling the SPI: set all bits needed in SPCR except the SPE bit, then set SPE.

2. Enable the master SPI prior to selecting the slave device (SS low).

Table 17-2.

SPDR – SPI Data Register

SPDR Address = EAH

Reset Value= 00H (after cold reset)

unchanged (after warm reset)

Not Bit Addressable

SPD7

SPD6

SPD5

SPD4

SPD3

SPD2

SPD1

SPD0

Bit

76543210

Writes to SPDR load the transmit buffer. In Master mode, a write also starts a transfer if the master is currently idle.

In Slave mode, if data is not loaded to SPDR the SPI will echo the last byte received on the next transfer. Reads

from SPDR return the value of the receive buffer, which is the last byte received. If SPDR is not read before

completion of the next transfer, the old value will be lost.

Table 17-3.

SPCR – SPI Control Register

SPCR Address = E9H

Reset Value = 0000 0000B

Not Bit Addressable

TSCK

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

765432

Symbol

Function

TSCK

SCK Clock Mode. When TSCK = 0, the SCK baud rate is based on the system clock, divided by the SPR

1-0 ratio.When

TSCK = 1, the SCK baud rate is based on the Timer 1 overflow rate, divided by the SPR1-0 ratio.

SPE

SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and

P1.7. SPI = 0 disables the SPI channel.

DORD

Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.

MSTR

Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects slave SPI mode.

CPOL

Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

transmitting. Please refer to Figure 23-9 on SPI clock phase and polarity control.

CPHA

Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and

slave. Please refer to Figure 23-9 on SPI clock phase and polarity control.

SPR0

SPR1

SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no

effect on the slave. The relationship between SCK and the oscillator frequency, f

OSC., is as follows:

SPR1

SPR0

SCK (TSCK = 0)

SCK (TSCK = 1)

OSC/4

fT1OVF/4

OSC/8

T1OVF/8

OSC/32

fT1OVF/32

OSC/64

fT1OVF/64

AT89LP428 Datasheet(PDF) 97 Page - ATMEL Corporation

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