EM68932DVKB datasheet(40/40 Pages) ETRON

No. de pieza	EM68932DVKB

Descripción Electrónicos	4M x 32 Mobile DDR Synchronous DRAM (SDRAM)

PDF	40 Pages

Scroll/Zoom	100%

Fabricante Electrónico	ETRON [Etron Technology, Inc.]

Página de inicio	http://www.etron.com

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EtronTech

EM68932DVKB

Etron Confidential

Rev. 1.0

Aug. 2009

Figure 37. Power-Down Entry and Exit

High-Z

PRE

NOP

tRP

Don’t Care

NOP

Pre All

tCKE

tXP

A10 (AP)

Address

Command

CKE

Valid

Power Down

Entry

Exit From

Power Down

Any

Command

Precharge Power-Down mode shown: all banks are idle and tRP is met

when Power-Down Entry command is issued

Figure 38. Deep Power-Down Entry and Exit

Don’t Care

NOP

DPD

NOP

Valid

(1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling

within specifications by Ta0

(2) Device must be in the all banks idle state prior to entering Deep Power-Down mode

(3) 200µs is required before any command can be applied upon exiting Deep Power-Down mode

(4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed

by two AUTO REFRESH commands and a load mode register sequence

tRP

Ta0

Ta1

Ta2

Address

Command

DQS

CKE

Enter DPD Mode

Exit DPD Mode

T = 200µs

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