EM6819 datasheet(13/154 Pages) EMMICRO

13 / 154 page

EM6819

07 /09 – rev.D

www.emmicroelectronic.com

Clock selection, clock switching and system pheripherals

This block takes care of all internal and external clock sources. It synchronizes the clocks where needed and assures

that the system can not hang-up due to faulty clock switching (i.e avoids switching to a non-present clock source). This

block is also an essential part of the low power architecture by minimizing the total energy consumption by keeping the

active clocking nodes to a strict minimum.

Digital and Analog internal peripherals

This part contains all the user peripherals such as timer, SPI, ADC, etc … These peripherals are user configurable and

fully adjustable to the user application.

Communication interfaces via the IO pads

Here are all the external communication channels grouped. All communication goes through at least 1 of the max 24

IO’s. Several internal functions such as, serial interface, PWM, freq outputs, etc. are mapped to the IO’s.

2.1 OPERATING MODES

The circuit has 4 distinctive operations modes wheras Standby, Sleep and Power-Down mode are specific low power

modes

Active

CPU running all functions may be used

StandBy

CPU in Standby not clocked. Peripheral functions may be running

Sleep

CPU in Standby not clocked. Peripherals stopped except for specifically enabled functions

Power-Down

CPU and peripheral functions in reset. No Clocks. Pad configuration maintained.

2.1.1

ACTIVE MODE

The active mode is the default mode after any system reset. In this mode all peripherals are powered and ready to be

used. All Low power modes are initiated from the actice mode by executing the HALT instruction.

If using an external high frequency clock input and the derived CPU clock is higher 6MHz the user shall set the bit

FrcFastRead which acts as a booster for the Flash reading. For all internal clock selection the boosting is done

automatically.

2.2 LOW POWER MODES

The Low power modes are enabled by the CPU HALT instruction execution. The resulting Low power mode selection

then depends on the SelPwrDwn and SelSleep bit settings, both are located in the system register RegSysCfg1.

Mode

HALT Instruction

RegSysCfg1.SelSleep

RegSysCfg1.SelPwrDwn

Active

StandBy

Yes

Sleep

Yes

Power-Down

Yes

2.2.1

STANDBY MODE

This mode is activated by HALT instruction if SelPwrDwn=’0’ and SelSleep=’0’.

The active clock oscillator for the CPU clock source as selected by SelCkCR will be disabled in StandBy mode if it is not

used by other block/peripheral or it’s not forced-on. The Flash memory is disabled to save power.

If fast wake-up is needed the user can choose to leave the Flash memory enabled in StandBy mode by setting the bit

StdByFastWkUp in register RegSysCfg1 to ‘1’.

Resume from standby mode and going back to active mode with an Event, an Interrupt or a system reset.

Wake-up time from Standby mode is 1.5us if StdByFastWkUp =’1’ and CPU is on 15 MHz with the 15 MHz RC

oscillator forced on.

Wake-up time from Standby mode is 10us if StdByFastWkUp =’1’ and CPU is on 2 MHz with the 2 MHz RC oscillator

forced on.

Wake-up time from Standby mode is 150us if StdByFastWkUp =’0’ and CPU is on 2 MHz with the 2 MHz RC oscillator

forced on.

Wake-up delay is measured from the time of the wake-up event until the result of the first CPU instruction.

EM6819 Datasheet(PDF) 13 Page - EM Microelectronic - MARIN SA

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