MFRC522 datasheet(69/96 Pages) NXP

69 / 96 page

MFRC522_33

Product data sheet

PUBLIC

Rev. 3 — 26 October 2009

112133

69 of 96

NXP Semiconductors

MFRC522

Contactless reader IC

10.3.1.7

Receive

The MFRC522 activates the receiver path and waits for a data stream to be received. The

correct settings must be chosen before starting this command.

This command automatically terminates when the data stream ends. This is indicated

either by the end of frame pattern or by the length byte depending on the selected frame

type and speed.

Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive

command will not automatically terminate. It must be terminated by starting another

command in the CommandReg register.

10.3.1.8

Transceive

This command continuously repeats the transmission of data from the FIFO buffer and the

reception of data from the RF ﬁeld. The ﬁrst action is transmit and after transmission the

command is changed to receive a data stream.

Each transmit process must be started by setting the BitFramingReg register’s StartSend

bit to logic 1. This command must be cleared by writing any command to the

CommandReg register.

Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive

command never leaves the receive state because this state cannot be cancelled

automatically.

10.3.1.9

MFAuthent

This command manages MIFARE authentication to enable a secure communication to

any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the

FIFO buffer before the command can be activated:

• Authentication command code (60h, 61h)

• Block address

• Sector key byte 0

• Sector key byte 1

• Sector key byte 2

• Sector key byte 3

• Sector key byte 4

• Sector key byte 5

• Card serial number byte 0

• Card serial number byte 1

• Card serial number byte 2

• Card serial number byte 3

In total 12 bytes are written to the FIFO.

Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked.

However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set.

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