MCP3551-ESLASHMS datasheet(18/36 Pages) MICROCHIP

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MCP3550/1/3

DS21950E-page 18

4.4

Differential Analog Inputs

The MCP3550/1/3 devices accept a fully differential

analog input voltage to be connected to the VIN+ and

VIN- input pins. The differential voltage that is converted

is defined by VIN = VIN+ – VIN-. The differential voltage

range specified for ensured accuracy is from -VREF to

+VREF.

The converter will output valid and usable codes from

-112% to 112% of output range (see Section 5.0

“Serial Interface”) at room temperature. The ±12%

overrange is clearly specified by two overload bits in

the output code: OVH and OVL. This feature allows for

system calibration of a positive gain error.

The absolute voltage range on these input pins extends

from VSS - 0.3V to VDD + 0.3V. If the input voltages are

above or below this range, the leakage currents of the

ESD diodes will increase exponentially, degrading the

accuracy and noise performance of the converter. The

common mode of the analog inputs should be chosen

such that both the differential analog input range and

absolute voltage range on each pin are within the

specified operating range defined in Section 1.0

“Electrical Characteristics”.

Both the analog differential inputs and the reference

input have switched-capacitor input structures. The

input

capacitors

are

charged

and

discharged

alternatively with the input and the reference in order to

process a conversion. The charge and discharge of the

input capacitors create dynamic input currents at the

VIN+ and VIN- input pins inversely proportional to the

sampling capacitor. This current is a function of the

differential input voltages and their respective common

modes. The typical value of the differential input

impedance is 2.4 MΩ, with VCM = 2.5V, VDD = VREF =

5V. The DC leakage current caused by the ESD input

diodes, even though on the order of 1 nA, can cause

additional offset errors proportional to the source

resistance at the VIN+ and VIN- input pins.

From a transient response standpoint and as a first-

order approximation, these input structures form a

simple RC filtering circuit with the source impedance in

series with the RON (switched resistance when closed)

of the input switch and the sampling capacitor. In order

to ensure the accuracy of the sampled charge, proper

settling time of the input circuit has to be considered.

Slow settling of the input circuit will create additional

gain error. As a rule of thumb, in order to obtain 1 ppm

absolute measurement accuracy, the sampling period

must be 14 times greater than the input circuit RC time

constant.

4.5

Voltage Reference Input Pin

The MCP3550/1/3 devices accept a single-ended

external reference voltage, to be connected on the

VREF input pin. Internally, the reference voltage for the

ADC is a differential voltage with the non-inverting input

connected to the VREF pin and the inverting input

connected to the VSS pin. The value of the reference

voltage is VREF - VSS and the common mode of the

reference is always (VREF - VSS)/2.

The MCP3550/1/3 devices accept a single-ended

reference voltage from 0.1V to VDD. The converter

output noise is dominated by thermal noise that is

independent of the reference voltage. Therefore, the

output noise is not significantly improved by lowering

the reference voltage at the VREF input pin. However, a

reduced reference voltage will significantly improve the

INL performance since the INL max error is

proportional to VREF2 (see Figure 2-4).

The charge and discharge of the input capacitor create

dynamic input currents at the VREF input pin inversely

proportional to the sampling capacitor, which is a func-

tion of the input reference voltage. The typical value of

the single-ended input impedance is 2.4 MΩ, with

VDD =VREF = 5V. The DC leakage current caused by

the ESD input diodes, though on the order of 1 nA

typically, can cause additional gain error proportional to

the source resistance at the VREF pin.

4.6

Power-On Reset (POR)

The MCP3550/1/3 devices contain an internal Power-

On Reset (POR) circuit that monitors power supply

voltage VDD during operation. This circuit ensures

correct device start-up at system power-up and power-

down events. The POR has built-in hysteresis and a

timer to give a high degree of immunity to potential

ripple and noise on the power supplies, as well as to

allow proper settling of the power supply during power-

up. A 0.1 µF decoupling capacitor should be mounted

as close as possible to the VDD pin, providing additional

transient immunity.

The threshold voltage is set at 2.2V, with a tolerance of

approximately ±5%. If the supply voltage falls below

this threshold, the MCP3550/1/3 devices will be held in

a reset condition or in Shutdown mode. When the part

is in Shutdown mode, the power consumption is less

than 1 µA. The typical hysteresis value is around

200 mV in order to prevent reset during brown-out or

other glitches on the power supply.

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