Preliminary Technical Data

ADIS16220

Rev. PrE | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AIN2

NC

NC

RST

SCLK

DOUT

DIN

A

CS

ADIS16220

TOP

LOOK THROUGH

VIEW

(Not to Scale)

16

15

14

13

5

6

7

8

PIN 1

INDICATOR

NOTES

1. NC = NO CONNECT.

2. THIS IS NOT AN ACTUAL TOP VIEW, BECAUSE THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS

A LAYOUT VIEW THAT REPRESENTS THE PIN CONFIGURATION IF THE PACKAGE IS LOOKED

THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1

SCLK

I

SPI, Serial Clock.

2

DOUT

O2

SPI, Data Output.

3

DIN

I

SPI, Data Input.

4

CS

I

SPI, Chip Select.

5, 6

DIO1, DIO2

I/O

Digital Input/Output Pins.

7, 8, 10, 11

NC

N/A

No Connect.

9

RST

I

Reset, Active Low.

12

AIN2

I

Analog Input Channel 2.

13

VDD

S

Power Supply, 3.3 V.

14

AIN1

I

Analog Input Channel 1.

15

VREF

O

Voltage Reference for AIN1 and AIN2.

16

GND

S

Ground.

RECOMMENDED PAD LAYOUT

0.670

12×

1.127

16×

4.1865

8×

2.6955

8×

5.391

4×

8.373

2×

0.500

16×

9.2mm × 9.2mm STACKED LGA PACKAGE

Figure 5. Recommended of a Pad Layout