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CS5560 Datasheet(PDF) 22 Page - Cirrus Logic |
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CS5560 Datasheet(HTML) 22 Page - Cirrus Logic |
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22 / 32 page ![]() CS5560 22 DS713PP2 5/4/09 Figure 17 illustrates the noise floor of the converter from 0.1 Hz to 25 kHz. While the plot does exhibit some 1/f noise at lower frequencies, the noise floor is entirely free of spurious frequency content due to digital activity inside the chip. Figure 16 illustrates a noise histogram of 32,768 samples. -180 -160 -140 -120 -100 -80 -60 0.1 1 10 100 1k 10k 25k Frequency (Hz) Shorted Input 1M Samples @ 50 kSps 64 Averages Figure 17. Spectral Plot of Noise with Shorted Input 0 100 200 300 400 500 600 700 800 Output (Codes) Std. Dev. = 19.0 Max - Min = 178 Figure 18. Noise Histogram (32k Samples) |
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