CS5374 datasheet(11/44 Pages) CIRRUS

11 / 44 page

CS5374

DS862PP1

DIGITAL CHARACTERISTICS (CONT.)

Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically

enters a power-down state. See Power Supply Characteristics for typical power-down timing.

24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge,

synchronization instant (

t0) is on the next MCLK rising edge.

25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Input

MCLK Frequency

(Note 23)fMCLK

2.048

MHz

MCLK Duty Cycle

MCLKDTC

MCLK Rise Time

tRISE

MCLK Fall Time

tFALL

MCLK Jitter (in-band or aliased in-band)

MCLKIBJ

300

MCLK Jitter (out-of-band)

MCLKOBJ

Master Sync Input

MSYNC Setup Time to MCLK Falling

(Note 24)tMSS

366

MSYNC Period

(Note 24)tMSYNC

976

MSYNC Hold Time after MCLK Falling

(Note 24)tMSH

610

MDATA Output

MDATA Output Bit Rate

fMDATA

-512

kbits/s

MDATA Output One’s Density Range

(Note 22)MDAT1D

Full-scale Output Code, Offset Corrected

(Note 25)MDATFS

0xA2E736

0x5D18CA

MCLK

MSYNC

t 0

tMSS

1 / fMCLK

tMSYNC

tMSH

MDATA

MFLAG

1 / fMDATA

Figure 7. MCLK / MSYNC Timing Detail

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