TMC1103 datasheet(4/16 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC1103

Pin Descriptions

Pin Name

Pin Number

Value

Pin Function Description

A/D Converters

VINA, VINB,

VINC

12, 55, 48

RTX to

RBX

Analog Inputs. The input voltage conversion range lies between the

voltage applied to the RTX and RBX pins.

RTA, RTB, RTC

14, 53, 50

2.6V

Reference Voltage, Top Inputs. DC voltages applied to RTA, RTB

and RTC define highest value of VINX.

RBA, RBB, RBC

15, 52, 51

0.6V

Reference Voltage, Bottom Inputs. DC voltages applied to RBA,

RBB and RBC define lowest value of VINX.

CLKA, CLKB,

CLKC

9, 58, 45

CMOS

Clock Inputs. CMOS-compatible. VINX is sampled on the falling

edge of CLKX.

DA7-0

4, 3, 2, 80, 79,

78, 77, 76

CMOS/

TTL

Data outputs, Converter A (D7 = MSB). Eight-bit CMOS- and

TTL-compatible digital outputs. Valid data is output on the rising

edge of CLKX.

DB7-0

63, 64, 65, 66,

67, 68, 69, 70

CMOS/

TTL

Data outputs, Converter B (D7 = MSB). Eight-bit CMOS- and

TTL-compatible digital outputs. Valid data is output on the rising

edge of CLKX.

DC7-0

41, 40, 39, 38,

37, 36, 35, 34

CMOS/

TTL

Data outputs, Converter C (D7 = MSB). Eight-bit CMOS- and

TTL-compatible digital outputs. Valid data is output on the rising

edge of CLKX.

OEA, OEB, OEC

5, 62, 42

CMOS

Output Enable Inputs. CMOS-compatible. When LOW, the A/D

output is enabled. When HIGH, the output is in a high-impedance

state.

Clamps

VCLPA, VCLPB,

VCLPB

16, 17, 18

RTX to

RBX

Clamp Reference Voltage. One reference for each clamp. A VINX

input is clamped to VCLPX when CLPX is low.

CLPA, CLPB,

CLPC

28, 29, 30

CMOS

Clamp Pulse Inputs. One input for each A/D clamp. When CLPX is

low, the VINX input is clamped to the VCLPX clamp voltage.

Power

VDDA

11, 47, 56

+5V

Analog Supply Voltage. +5 Volt power inputs. These should come

from the same power source and be decoupled to AGND.

VDD

6, 7, 27, 28, 29,

30, 43, 44, 60,

+5V

Digital Supply Voltage. +5 Volt power inputs. These should come

from the same power source and be decoupled to AGND.

AGND

13, 49, 54

0.0V

Analog Ground. Ground connections. These pins should be

connected to the system analog ground plane.

DGND

16, 17, 18, 19,

20, 21, 22, 25,

26, 32, 33, 71,

72, 74, 75

0.0V

Digital Ground. Ground connections. These pins should be

connected to the system analog ground plane.

No Connect

N/C

1, 8, 10, 23, 24,

31, 46, 57, 59,

open

Not Connected.

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