8

3/5/02

SPT7937

Figure 4 – Simplified Reference Ladder Drive Circuit

Without Force/Sense Circuit

R/2

R

R

R

R

R

R

R/2

R=30 W (typ)

All capacitors are 0.01 µF

0.0 V

(0.075 V)

(+3.91 V)

21 mV

50 mV

+4.0 V

External

Reference

In cases in which wider variations in offset and gain can be

force and sense lines to AGND with a 0.01 µF capacitor

(chip cap preferred) to minimize high-frequency noise in-

jection. If this simplified configuration is used, the following

considerations should be taken into account:

The reference ladder circuit shown in figure 4 is a simpli-

fied representation of the actual reference ladder with

force and sense taps shown. Due to the actual internal

equal:

equal:

Figure 4 shows an example of expected voltage drops for

ANALOG INPUT

with respect to the voltage reference. (See the Voltage

Reference section.)

The drive requirements for the analog inputs are very mini-

mal when compared to most other converters due to the

SPT7937’s extremely low input capacitance of only 5 pF

and very high input resistance in excess of 35 k

Ω.

The analog input should be protected through a series re-

sistor and diode clamping circuit as shown in figure 5. To

prevent possible latch-up condition, the power supplies

must be powered up before the input is applied.

CALIBRATION

The SPT7937 uses a user-transparent, auto-calibration

scheme to ensure 12-bit accuracy over time and tempera-

ture. Gain and offset errors are continually adjusted to

12-bit accuracy during device operation.

Upon powerup, the SPT7937 begins its calibration algo-

rithm. In order to achieve the calibration accuracy required,

the offset and gain adjustment step size is a fraction of a

12-bit LSB. Since the calibration algorithm is an over-

sampling process, a minimum of 10,000 clock cycles are

required. This results in a minimum calibration time upon

powerup of 357 µsec (for a 28 MHz clock). Once cali-

brated, the SPT7937 remains calibrated over time and

temperature.

Since the calibration cycles are initiated on the rising edge

of the clock, the clock must be continuously applied for the

SPT7937 to remain in calibration.

Figure 5 – Recommended Input Protection Circuit

47 W

D1

D2

ADC

Buffer

+V

–V

D1 = D2 = Hewlett Packard HP5712 or equivalent