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8/21/01

SPT7863

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the

stated device performance. Figure 2 shows the typical in-

terface requirements when using the SPT7863 in normal

circuit operation. The following sections provide descrip-

tions of the major functions and outline critical perfor-

mance criteria to consider for achieving the optimal device

performance.

POWER SUPPLIES AND GROUNDING

ply voltages on the SPT7863 be derived from a single ana-

should be used for all interface circuitry. Fairchild suggests

latch-up condition on powerup.

OPERATING DESCRIPTION

The general architecture for the CMOS ADC is shown in

the block diagram. The design contains 16 identical suc-

cessive approximation ADC sections, all operating in par-

allel, a 16-phase clock generator, an 11-bit 16:1 digital

output multiplexer, correction logic, and a voltage refer-

ence generator that provides common reference levels for

each ADC section.

The high sample rate is achieved by using multiple SAR

ADC sections in parallel, each of which samples the input

signal in sequence. Each ADC uses 16 clock cycles to

complete a conversion. The clock cycles are allocated as

shown in table II.

Figure 2 – Typical Interface Circuit

CLK

DAV

D10

D1

EN

Ref In

(+4 V)

CLK IN

Enable/Tri-State

(Enable = Active Low)

Interfacing

Logics

SPT7860

DGND

+

10 µF

+5 V

Digital

+5 V

Digital

RTN

3.3/5

L1

NOTES: 1) L1 is to be located as closely to the device as possible.

2) All capacitors are 0.1 µF surface-mount unless otherwise specified.

3) L1 is a 10 µH inductor or a ferrite bead.

+A5

AGND

+

10 µF

+5 V

Analog

+5 V

Analog

RTN

+A5

*To reduce the possibility of latch-up, avoid

connecting the DGND pins of the ADC to the

digital ground of the system.

3.3/5

3.3/5

D9

D8

D7

D6

D5

D4

D3

D2

D0

DGND

SPT7863

log supply as shown in figure 2. A separate digital supply

using this power supply configuration to prevent a possible

CADEKA suggests that both the digital and the analog sup-