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SPT7734

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the

stated device performance. Figure 1 shows the typical inter-

face requirements when using the SPT7734 in normal circuit

operation. The following sections provide descriptions of the

major functions and outline critical performance criteria to

consider for achieving the optimal device performance.

Figure 1 - Typical Interface Circuit

The high sample rate is achieved by using multiple SAR ADC

sections in parallel, each of which samples the input signal in

sequence. Each ADC uses 16 clock cycles to complete a

conversion. The clock cycles are allocated as follows:

Table II - Clock Cycles

Clock

Operation

1

Reference zero sampling

2

Auto-zero comparison

3

Auto-calibrate comparison

4

Input sample

5-15

9-bit SAR conversion

16

Data transfer

The 16 phase clock, which is derived from the input clock,

synchronizes these events. The timing signals for adjacent

ADC sections are shifted by one clock cycle so that the analog

input is sampled on every cycle of the input clock by exactly

one ADC section. After 16 clock periods, the timing cycle

repeats. The latency from analog input sample to the corre-

sponding digital output is 12 clock cycles.

• Since only 16 comparators are used, a huge power savings

is realized.

• The auto-zero operation is done using a closed loop

system that uses multiple samples of the comparators

response to a reference zero.

• The auto-calibrate operation, which calibrates the gain

of the MSB reference and the LSB reference, is also

done with a closed loop system. Multiple samples of the

gain error are integrated to produce a calibration voltage for

each ADC section.

• Capacitive displacement currents, which can induce sam-

pling error, are minimized since only one comparator

samples the input during a clock cycle.

• The total input capacitance is very low since sections of the

converter which are not sampling the signal are isolated

from the input by transmission gates.

VOLTAGE REFERENCE

The SPT7734 requires the use of a single external voltage

reference for driving the high side of the reference ladder. It

must be within the range of 3 V to 5 V. The lower side of the

ladder is typically tied to AGND (0.0 V), but can be run up to

2.0 V with a second reference. The analog input voltage

range will track the total voltage difference measured be-

Force and sense taps are provided to ensure accurate and

stable setting of the upper and lower ladder sense line

voltages across part-to-part and temperature variations. By

using the configuration shown in figure 2, offset and gain

errors of less than

±2 LSB can be obtained.

POWER SUPPLIES AND GROUNDING

voltages on the SPT7734 be derived from a single analog

supply as shown in figure 1. A separate digital supply should

this power supply configuration to prevent a possible latch-

up condition on power up.

OPERATING DESCRIPTION

The general architecture for the CMOS ADC is shown in the

block diagram. The design contains 16 identical successive

approximation ADC sections, all operating in parallel, a 16-

phase clock generator, an 9-bit 16:1 digital output multi-

plexer, correction logic, and a voltage reference generator

which provides common reference levels for each ADC section.

VRHF

VRLS

VRLF

VRHS

VIN

CLK

VCAL

DAV

D8

D0

EN

AVDD

AGND

DGND* DVDD

Ref In

(+4 V)

VIN

CLK IN

Enable/Tri-State

(Enable = Active Low)

Interfacing

Logics

+D5

SPT7734

DGND

+

10 µF

+5 V

Digital

+5 V

Digital

RTN

+D5

FB3

NOTES: 1) FB3 is to be located as closely to the device as possible.

2) There should be no additional connections to the right of FB1 and FB2.

3) All capacitors are 0.1 µF surface-mount unless otherwise specified.

4) FB1, FB2 and FB3 are 10 µH inductors or ferrite beads.

FB1

FB2

+A5

AGND

+

10 µF

+5 V

Analog

+5 V

Analog

RTN

+A5

*To reduce the possibility of latch-up, avoid

connecting the DGND pins of the ADC to the

digital ground of the system.

CADEKA suggests that both the digital and the analog supply

be used for all interface circuitry. CADEKA suggests using