System features introduction

STA2065

14/20

Doc ID16050 Rev 1

3.3

Frequency and power range

The core voltage range is 1.25 ±4 %V while the IO voltage ranges are 1.8 ±10 %V,

2.5 ± 10 %V and 3.3 ± 10 %V.

Table 2 shows some power use cases of STA2065 in NORMAL mode:

The background of Table 2 is the maximization of data throughput on the DRAM interface,

matching the currently available DRAM speed grades: 133 MHz, 166 MHz and 200 MHz (LP

DDR) and 333 MHz (DDR2). Despite this, it is possible to program the ARM core, the

internal bus and the DDR to run at different speeds than the ones mentioned in Table 2 The

ARM bus clock and the bus clock are derived from the same common source (VCO of the

PLL1) but are asynchronous each other. The DDR frequency can be the same

(synchronous) or derived with a different prescaling (1,2,3,4,5,6,8,9 or 10) from the VCO of

PLL1 or PLL2 (asynchronous configuration).

STA2065 embeds a complete GPS subsystem where both gate logic and dedicated DSP

work together. There are specific constraints in this subsystem in terms of minimum

frequency in order to guarantee the target GPS specifications.

current drawn is 20

μA. In this state, the clock is not running and the current leakage is

mainly due to the Backup memory. The 20

μA current limit has to be considered with

equal to the junction temperature).

Table 2.

Frequency and power use cases

Core Freq

[MHz]

Bus Freq

[MHz]

DDR Freq

[MHz]

Sync/Async

[S/A]

1.2 5(±4%)

624

208

312

A, DDR2

1.2 5(±4%)

624

156

156

S

1.2 5(±4%)

624

124.8

124.8

S

1.2 5(±4%)

533

177.67

177.67

S

1.2 5(±4%)

533

133.25

133.25

S

1.2 5(±4%)

533

177.67

312

A, DDR2

1.2 5(±4%)

520

208

130

A

1.2 5(±4%)

520

173.34

173.34

S

1.2 5(±4%)

520

130

130

S

1.2 5(±4%)

520

208

312

A, DDR2

1.2 5(±4%)

494

197.6

197.6

S

1.2 5(±4%)

494

164.67

164.67

S

1.2 5(±4%)

494

123.5

123.5

S

1.2 5(±4%)

494

208

329.34

A, DDR2