January 2007

PCS809/PCS810

rev 0.2

3 of 8

Notice: The information in this document is subject to change without notice.

Detailed Description

RESET OUTPUT

µP will be activated at a valid reset state. These µP

supervisory circuits assert reset to prevent code execution

errors during power-up, power-down, or brownout

conditions.

RESET

is

guaranteed

to

be

a

logic

low

for

V

an internal timer keeps RESET low for the reset timeout

period; after this interval, RESET goes high.

If a brownout condition occurs (VCC drops below the reset

threshold), RESET goes low. Any time VCC goes below

the reset threshold, the internal timer resets to zero, and

RESET goes low. The internal timer is activated after VCC

returns above the reset threshold, and RESET remains

low for the reset timeout period.

BENEFITS

OF

HIGHLY

ACCURATE

RESET

THRESHOLD

PCS809/810 with specified voltage as 5V±10% or

3V±10% are ideal for systems using a 5V±5% or 3V±5%

power supply. The reset is guaranteed to assert after the

power supply falls out of regulation, but before power

drops below the minimum specified operating voltage

range of the system ICs. The pre-trimmed thresholds are

reducing the range over which an undesirable reset may

occur.

Application Information

NEGATIVE-GOING VCC TRANSIENTS

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, PCS809 series are

relatively resistant to short-duration negative-going VCC

transient.

ENSURING A VALID RESET OUTPUT DOWN TO

VCC=0

When VCC falls below 0.9V, PCS809 RESET output no

longer sinks current; it becomes an open circuit. In this

case, high-impedance CMOS logic inputs connecting to

RESET can drift to undetermined voltages. Therefore,

PCS809/810 with CMOS is perfect for most applications of

VCC below 0.9V. However in applications where RESET

must be valid down to 0V, adding a pull-down resistor to

RESET causes any leakage currents to flow to ground,

holding RESET low.

INTERFACING TO µP WITH BIDIRECTIONAL RESET

PINS

The RESET output on the PCS809 is open drain, this

device interfaces easily with µPs that have bidirectional

reset pins. Connecting the µP supervisor’s RESET output

directly to the microcontroller’s RESET pin with a single

pull-up resistor allows either device to assert reset.