TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

13

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

UCAS

LCAS

Address

W

DQ8 – DQ15

OE

tWC

tRAS

tT

tRCD

tCRP

tRP

tCP

tASR

tRAD

tRAH

tASC

tWCS

tWP

tDS

Valid Data In

Row

Column

Don’t Care

Don’t Care

tCAS

tRSH

Don’t Care

tCWL

tCLCH

(see Note A)

Don’t Care

DQ0 – DQ7

tDH

tDS

Valid Data In

Don’t Care

tCSH

tCAL

tRAL

tDH

tRWL

tCAH

tWCH

tWCS

(see Note C)

(see Note C)

tWCH (see Note C)

Don’t Care

Don’t Care

Don’t Care

(see Note D)

(see Note D)

(see Note D)

(See Note C)

(see Note E)

tCAS

See Note E

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.

B. xCAS order is arbitrary.

C. tWCS and tWCH must be satisfied for each xCAS.

D. tDS and tDH of a DQ input are referenced to the corresponding xCAS.

E. tCWL must be satisfied for each xCAS to write properly to each byte.

Figure 5. Early-Write-Cycle Timing