TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

2

POST OFFICE BOX 655303

functional block diagram

Internal

Clock

CLK

CS

RD

INT/EOC

MUX

8-BIT

SAR ADC

Input Registers

and Control Logic

WR

CSTART

REFP

Three

State

Latch

AVDD

D0 – D5

D6/A0

D7/A1

REFM

DVDD

DGND

AGND

AIN

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AGND

21

Analog ground

AIN

23

I

ADC analog input

AVDD

22

Analog supply voltage, 2.7 V to 5.5 V

A0/D6

16

I/O

Bidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 for

initialization.

A1/D7

17

I/O

Bidirectional 3-state data bus. D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 for

initialization.

CLK

4

I

External clock input

CS

1

I

Chip select. A logic low on CS enables the TLV571.

CSTART

18

I

Hardware sample and conversion start input. The falling edge of CSTART starts sampling and the rising edge

of CSTART starts conversion.

DGND

5, 8, 9

Digital ground

DVDD

6

Digital supply voltage, 2.7 V to 5.5 V

D0 – D5

10 –15

I/O

Bidirectional 3-state data bus

INT/EOC

7

O

End-of-conversion/interrupt

NC

24

Not connected

RD

3

I

Read data. A falling edge on RD enables a read operation on the data bus when CS is low.

REFM

20

I

Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be grounded.

REFP

19

I

Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by the difference

between the voltage applied to REFP and REFM.

WR

2

I

Write data. A rising edge on the WR latches in configuration data when CS is low. When using software

conversion start, a rising edge on WR also initiates an internal sampling start pulse. When WR is tied to ground,

the ADC in nonprogrammable (hardware configuration mode).