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TLE206X Datasheet(PDF) 31 Page - Texas Instruments |
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TLE206X Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 75 page  TLE206x, TLE206xA, TLE206xB EXCALIBUR JFET INPUT HIGHOUTPUT DRIVE µPOWER OPERATIONAL AMPLIFIERS SLOS193B − FEBRUARY 1997 − REVISED MAY 2004 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLE2062Y electrical characteristics at VCC± = ±15 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TLE2062Y UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input offset voltage 0.9 4 mV αVIO Input offset voltage long-term drift (see Note 4) VIC = 0, RS = 50 Ω 0.04 µV/mo IIO Input offset current VIC = 0, RS = 50 Ω 2 pA IIB Input bias current 4 pA −11 −12 VICR Common-mode input voltage range −11 to −12 to V VICR Common-mode input voltage range to 13 to 16 V VOM + Maximum positive peak output voltage swing RL = 10 kΩ 13.2 13.7 V VOM + Maximum positive peak output voltage swing RL = 600 Ω 12.5 13.2 V VOM − Maximum negative peak output voltage swing RL = 10 kΩ − 13.2 − 13.7 V VOM − Maximum negative peak output voltage swing RL = 600 Ω − 12.5 −13 V VO = ±10 V, RL = 10 kΩ 30 230 AVD Large-signal differential voltage amplification VO = 0 to 8 V, RL = 600 Ω 25 100 V/mV AVD Large-signal differential voltage amplification VO = 0 to − 8 V, RL = 600 Ω 3 25 V/mV ri Input resistance 1012 Ω ci Input capacitance 4 pF zo Open-loop output impedance IO = 0 560 Ω CMRR Common-mode rejection ratio VIC = VICRmin, RS = 50 Ω 72 90 dB kSVR Supply-voltage rejection ratio ( ∆VCC/∆VIO) VCC ± = ±5 V to ±15 V, 75 93 dB kSVR Supply-voltage rejection ratio ( ∆VCC/∆VIO) VCC ± = ±5 V to ±15 V, RS = 50 Ω 75 93 dB ICC Supply current VO = 0, No load 625 690 µA NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated to TA = 25 °C using the Arrhenius equation and assuming an activation energy of 0.96 eV. TLE2062Y operating characteristics at VCC± = ±15 V, TA = 25°C PARAMETER TEST CONDITIONS TLE2062Y UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SR Slew rate at unity gain (see Figure 1) RL = 10 kΩ, CL = 100 pF 2.6 3.4 4 V/ µs Vn Equivalent input noise voltage (see Figure 2) f = 10 Hz, RS = 20 Ω 70 nV/ √Hz Vn Equivalent input noise voltage (see Figure 2) f = 1 kHz, RS = 20 Ω 40 nV/ √Hz VN(PP) Peak-to-peak equivalent input noise voltage f = 0.1 Hz to 10 Hz 1.1 µV In Equivalent input noise current f = 1 Hz 1.1 fA/ √Hz THD Total harmonic distortion VO(PP) = 2 V, AVD = 2, RL = 10 kΩ, f = 10 kHz 0.025% B1 Unity-gain bandwidth (see Figure 3) RL = 10 kΩ, CL = 100 pF 2 MHz B1 Unity-gain bandwidth (see Figure 3) RL = 600 Ω, CL = 100 pF 1.5 MHz Settling time 0.1% 5 s Settling time 0.01% 10 µs BOM Maximum output-swing bandwidth AVD = 1, RL = 10 kΩ 40 kHz φm Phase margin at unity gain (see Figure 3) RL = 10 kΩ, CL = 100 pF 60 ° φm Phase margin at unity gain (see Figure 3) RL = 600 Ω, CL = 100 pF 70 ° |
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