SN74ACT3638

512

× 32 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS228D – JUNE 1992 – REVISED APRIL 1998

17

POST OFFICE BOX 655303

CLKB

IRA

B0 – B31

MBB

ENB

CSB

W/RB

ORB

CLKA

CSA

W/RA

MBA

ENA

A0 – A31

tsu(EN)

th(EN)

tc

th(EN)

tsu(EN)

tpd(C-IR)

FIFO1 Full

tc

tsk1†

ta

Previous Word in FIFO1 Output Register

Next Word From FIFO1

To FIFO1

Low

Low

High

Low

High

th(EN)

tsu(EN)

th(D)

tsu(D)

High

tpd(C-IR)

12

RDYA

tpd(C-R)

tpd(C-R)

tw(CLKL)

tw(CLKH)

tw(CLKL)

tw(CLKH)

† tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition high in the next CLKA cycle. If the time

between the rising CLKB edge and rising CLKA edge is less than tsk1, then IRA may transition high one CLKA cycle later than shown.

Figure 9. IRA-Flag Timing and First Available Write When FIFO1 Is Full