SN54HC10, SN74HC10

TRIPLE 3-INPUT POSITIVE-NAND GATES

SCLS083B – DECEMBER 1982 – REVISED MAY 1997

1

POST OFFICE BOX 655303

Small-Outline (D) and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J)

300-mil DIPs

description

These devices contain three independent 3-input

NAND gates. They perform the Boolean function

Y = A

• B • C or Y = A + B + C in positive logic.

The SN54HC10 is characterized for operation

over the full military temperature range of –55

°C

to 125

°C. The SN74HC10 is characterized for

operation from –40

°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

C

Y

H

H

H

L

L

XX

H

X

LX

H

X

X

L

H

1

1A

2

1B

1Y

12

13

1C

3

2A

5

2C

9

3A

2Y

6

10

3B

11

3C

3Y

8

&

4

2B

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, N, and W packages.

logic diagram (positive logic)

A

C

Y

B

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

2A

2B

2C

2Y

GND

1C

1Y

3C

3B

3A

3Y

SN54HC10 . . . J OR W PACKAGE

SN74HC10 ...D OR N PACKAGE

(TOP VIEW)

32 1 20 19

910 11 1213

4

5

6

7

8

18

17

16

15

14

1Y

NC

3C

NC

3B

2A

NC

2B

NC

2C

SN54HC10 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

Copyright

© 1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.