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EP1C20F Datasheet(PDF) 21 Page - Altera Corporation |
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EP1C20F Datasheet(HTML) 21 Page - Altera Corporation |
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21 / 106 page  Altera Corporation 2–15 May 2008 Preliminary MultiTrack Interconnect Figure 2–10. LUT Chain and Register Chain Interconnects The C4 interconnects span four LABs or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2–11 shows the C4 interconnect connections from a LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including PLLs, M4K memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. LE 1 LE 2 LE 3 LE 4 LE 5 LE 6 LE 7 LE 8 LE 9 LE 10 LUT Chain Routing to Adjacent LE Local Interconnect Register Chain Routing to Adjacent LE's Register Input Local Interconnect Routing Among LEs in the LAB |
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