FD51xxT-32.768KHz

CMOS Clock Oscillator

March 2009

www.pletronics.com

425-776-1880

3

PLL Multiplier #1.

The device can make only one of the setting of connections shown in the block diagram (only one

pattern stored in eePROM).

Control Inputs

The two inputs, S1/SDA and S2/SCL can be configured in two ways.

1)

Used as 2 user inputs to permit up to 4 states, Sx input setting.

2)

The SDA and SCL become clock and data inputs to write to the FD5T internal setting memory.

The interface follows the I

sets the operation. (Not allowed if the VCXO function is specified.)

Standard Configuration

S1

S2

Output

SS

PLL

Low

Low

Tri State

---

Disable

High

Low

32.768KHz

±1% centered

Enable

Low

High

32.768KHz

±2% centered

Enable

High

High

32.768KHz

none

Disable