LTC3524 datasheet(13/16 Pages) LINER

13 / 16 page

LTC3524

3524f

and VH should be at least 0.47μF. Please be certain that

the capacitors used are rated for the maximum voltage

with adequate safety margin. Refer to Table 2 for a listing

of capacitor vendors.

Table 2. Capacitor Vendor Information

Supplier

Phone

Website

AVX

(803) 448-9411

www.avxcorp.com

Murata

(714) 852-2001

www.murata.com

Samsung

(408) 544-5200

www.sem.samsung.com

Taiyo Yuden

(800) 368-2496

www.t-yuden.com

TDK

(847) 803-6100

www.component.tdk.com

APPLICATIONS INFORMATION

Figure 4. Suggested Layout Two Layer Board (Not to Scale)

Printed Circuit Board Layout Guidelines

High-speed operation of the LTC3524 demands care-

ful attention to PCB layout. You will not get advertised

performance with a careless layout. Figure 4 shows the

recommended component placement for a double layer

PCB. The bottom layer is used as a common ground plane

except for the VN trace.

VOUT

LAYOUT NOTES:

*KEEP RPROG AWAY FROM SW2 TRACES

LIGHT GREY TOP LAYER

VIA TO BOTTOM GROUND PLANE.

GROUND PLANE FILLS BOTTOM

VIN

COMPONENT AND IC SIZES

NOT TO SCALE

TOP VIEW

LED2

–

FBH

FBN

ELED1

PROG

ELED2

SW2

VLED

LED1

ELED1 ELED2

ELCD

GND

WHITE LEDs

SCHOTTKY DIODE

WHITE LEDs

C2+

V2x

VNIN

CN+

ELCD

VIN

FBVO

VOUT

SW1

C2–

3524 F04

SCHOTTKY

DIODE

LTC3524 Datasheet(PDF) 13 Page - Linear Technology

LTC3524 Datasheet(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Datasheet Descarga

Enlace URL