LTC1863L/LTC1867L

13

1863L7Lf

If the CS/CONV returns low during a bit decision, it can

create a small error. For best performance ensure that the

CS/CONV returns low either within 100ns after the conver-

sion starts (i.e. before the first bit decision) or after the

conversion ends. If CS/CONV is low when the conversion

ends, the MSB bit will appear on SDO at the end of the

conversion and the ADC will remain powered up.

Sleep Mode

If the SLP = 1 is selected in the input word, the ADC will

enter SLEEP mode and draw only leakage current (pro-

release from the SLEEP mode, the ADC needs 80ms to

wake up (charge the 2.2µF/10µF bypass capacitors on

Board Layout and Bypassing

To obtain the best performance, a printed circuit board

with a ground plane is required. Layout for the printed

circuit board should ensure digital and analog signal lines

are separated as much as possible. In particular, care

should be taken not to run any digital signal alongside an

analog signal.

plane as close to the pin as possible; the low impedance of

APPLICATIO S I FOR ATIO

the common return for these bypass capacitors is essen-

tial to the low noise operation of the ADC. The width for

these tracks should be as wide as possible.

Timing and Control

Conversion start is controlled by the CS/CONV digital

input. The rising edge transition of the CS/CONV will start

a conversion. Once initiated, it cannot be restarted until the

conversion is complete. Figures 6 and 7 show the timing

diagrams for two types of CS/CONV pulses.

Example 1 (Figure 6) shows the LTC1863L/LTC1867L

operating in automatic nap mode with CS/CONV signal

staying HIGH after the conversion. Automatic nap mode

provides power reduction at reduced sample rate.

The ADCs can also operate with the CS/CONV signal

returning LOW before the conversion ends. In this mode

(Example 2, Figure 7), the ADCs remain powered up. The

digital output, SDO, will go HIGH immediately after the

conversion is complete if the analog inputs are above half

scale in unipolar mode or below half scale in bipolar mode.

This is a way to measure the conversion time of the A/D

converter.

Figures 8 and 9 are the transfer characteristics for the

bipolar and unipolar mode.

S0

SD

0S

S1

COM

UNI

SLP

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CS/CONV

SCK

SDI

SDO

(LTC1863L)

Hi-Z

D12

D15

D14

D13

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Hi-Z

123456789

10

11

12

13

14

15

16

1867 F06

DON'T CARE

DON'T CARE

NOT NEEDED FOR LTC1863L

NAP MODE

SDO

(LTC1867L)

MSB

MSB

Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV

Remaining HIGH after the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate