LT3472

9

3472f

Figure 7. Recommended Component Placement

APPLICATIO S I FOR ATIO

Figure 6. Start-Up Sequencing

the sum of the two outputs is always positive. The se-

quencing is shown in Figure 6.

Board Layout Consideration

As with all switching regulators, careful attention must be

paid to the PCB board layout and component placement.

To maximize efficiency, switch rise and fall times are made

as short as possible. To prevent electromagnetic interfer-

5V/DIV

5V/DIV

5V/DIV

100µs/DIV

3472 FO6

3472 F06

ence (EMI) problems, proper layout of the high frequency

switching path is essential. The voltage signals of the SWP

and SWN pins have rise and fall times of a few ns. Minimize

the length and area of all traces connected to the SWP and

SWN pins and always use a ground plane under the

switching regulator to minimize interplane coupling. Rec-

ommended component placement is shown in Figure 7.