9202 datasheet(165/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

Figure 85. Reset (RESET) Timing

Table 134. Reset (RESET) Timing (5V Devices)

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 135. Reset (RESET) Timing (3V Devices)

Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Table 136. VSTBYON Definitions Timing (5V Devices)

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Table 137. VSTBYON Timing (3V Devices)

Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET Active Low Time(1)

150

tNLNH–PO

Power-on Reset Active Low Time

tNLNH–A

Warm RESET (2)

µs

tOPR

RESET High to Operational Device

120

Symbol

Parameter

Conditions

Min

Max

Unit

tNLNH

RESET Active Low Time(1)

300

tNLNH–PO

Power-on Reset Active Low Time

tNLNH–A

Warm RESET (2)

µs

tOPR

RESET High to Operational Device

300

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tBVBH

VSTBY Detection to VSTBYON Output High

(Note 1)

µs

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

(Note 1)

µs

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tBVBH

VSTBY Detection to VSTBYON Output High

(Note 1)

µs

tBXBL

VSTBY Off Detection to VSTBYON Output

Low

(Note 1)

µs

tNLNH-PO

tOPR

AI02866b

RESET

tNLNH

tNLNH-A

tOPR

VCC

CC(min)

Power-On Reset

Warm Reset

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