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EPLD Datasheet(PDF) 19 Page - Altera Corporation

No. de pieza EPLD
Descripción Electrónicos  The Altera Classic device family offers a solution to high-speed, lowpower logic integration. Fabricated on advanced CMOS technology
PDF  42 Pages
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Fabricante Electrónico  ALTERA [Altera Corporation]
Página de inicio  http://www.altera.com
Logo ALTERA - Altera Corporation

EPLD Datasheet(HTML) 19 Page - Altera Corporation

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Altera Corporation
763
Classic EPLD Family Data Sheet
Notes to tables:
(1)
These values are specified in Table 3 on page 758.
(2)
See Application Note 78 (Understanding MAX 5000 & Classic Timing) in this data book for information on internal
timing parameters.
(3)
The non-Turbo adder must be added to this parameter when the Turbo Bit option is off.
(4)
Sample-tested only for an output change of 500 mV.
(5)
The fMAX values represent the highest frequency for pipelined data.
(6)
Measured with a device programmed as a 16-bit counter.
(7)
Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter
applies for both global and array clocking.
Table 11. EP610-25, EP610-30 & EP610-35 Internal Timing Parameters
Symbol
Parameter
Condition
EP610-25
EP610-30
EP610-35
Unit
Min
Max
Min
Max
Min
Max
tIN
Input pad and buffer delay
8.0
9.0
11.0
ns
tIO
I/O input pad and buffer delay
2.0
2.0
2.0
ns
tLAD
Logic array delay
11.0
14.0
15.0
ns
tOD
Output buffer and pad delay
C1 = 35 pF
6.0
7.0
9.0
ns
tZX
Output buffer enable delay
C1 = 35 pF
6.0
7.0
9.0
ns
tXZ
Output buffer disable delay
C1 = 5 pF
6.0
7.0
9.0
ns
tSU
Register setup time
11.0
11.0
12.0
ns
tH
Register hold time
10.0
10.0
10.0
ns
tIC
Array clock delay
13.0
16.0
17.0
ns
tICS
Global clock delay
1.0
1.0
0.0
ns
tFD
Feedback delay
3.0
5.0
8.0
ns
tCLR
Register clear time
13.0
16.0
17.0
ns



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