AT89C5122D-RDRUM datasheet(83/208 Pages) ATMEL

83 / 208 page

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Reset Value = 0XXX X001b

Reset Value = 0111 0100b

Table 51.

Smart Card ETU Register 1 - SCETU1 (S:ADh, SCRS=1)

COMP

ETU10

ETU9

ETU8

Bit Number

Bit Mnemonic

Description

7COMP

Compensation

Clear this bit when no time compensation is needed (i.e. when the ETU to Card CLK period ratio is close to an

integer with an error less than 1/4 of Card CLK period).

Set this bit otherwise and reduce the ETU period by 1 Card CLK cycle for even bits.

6-3

Reserved

The value read from these bits is indeterminate. Do not change these bits.

2-0

ETU[10:8]

ETU MSB

Used together with the ETU LSB in SCETU0 (Table 52)

Warning

: the ETU counter is reloaded at each register’s write operation.

Do not change this register during character reception or transmission or while Guard Time or Waiting Time

Counters are running.

Table 52.

Smart Card ETU Register 0 - SCETU0 (S:ACh, SCRS=1)

ETU7

ETU6

ETU5

ETU4

ETU3

ETU2

ETU1

ETU0

Bit Number

Bit Mnemonic

Description

7 - 0

ETU[7:0]

ETU LSB

The Elementary Time Unit is (ETU[10:0] - 0.5*COMP)/f, where f is the Card CLK frequency.

According to ISO 7816, ETU[10:0] can be set between 11 and 2048.

The default reset value of ETU[10:0] is 372 (F=372, D=1).

AT89C5122D-RDRUM Datasheet(PDF) 83 Page - ATMEL Corporation

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