CS49DV8C datasheet(17/30 Pages) CIRRUS

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DS868PP2

CS49DV8C Data Sheet

32-bit Audio DSP Family

5.12 Switching Characteristics — Serial Control Port - I2C Master Mode

Figure 6. Serial Control Port - I2C Master Mode Timing

Parameter

Symbol

Min

Max

Units

SCP_CLK frequency1

1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the

actual maximum speed of the communication port may be limited by the firmware application.

fiicck

-400

kHz

SCP_CLK low time

tiicckl

1.25

µs

SCP_CLK high time

tiicckh

1.25

µs

SCP_SCK rising to SCP_SDA rising or falling for START or

STOP condition

tiicckcmd

1.25

µs

START condition to SCP_CLK falling

tiicstscl

1.25

µs

SCP_CLK falling to STOP condition

tiicstp

2.5

µs

Bus free time between STOP and START conditions

tiicbft

µs

Setup time SCP_SDA input valid to SCP_CLK rising

tiicsu

100

Hold time SCP_SDA input after SCP_CLK falling

tiich

SCP_CLK low to SCP_SDA out valid

tiicdov

-18

SCP_CLK

SCP_SDA

tiicckl

tiicckh

tiicsu

tiich

R/W

ACK

LSB

ACK

MSB

tiicstp

tiicdov

tiicbft

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

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