TSA1203IF datasheet(12/20 Pages) STMICROELECTRONICS

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TSA1203 APPLICATION NOTE

DETAILED INFORMATION

The TSA1203 is a dual-channel, 12-bit resolution

high speed analog to digital converter based on a

pipeline structure and the latest deep sub micron

CMOS process to achieve the best performances

in terms of linearity and power consumption.

Each channel achieves 12-bit resolution through

the pipeline structure which consists of 12 internal

conversion stages in which the analog signal is

fed and sequentially converted into digital data. A

latency time of 7 clock periods is necessary to ob-

tain the digitized data on the output bus.

The input signals are simultaneously sampled on

both channels on the rising edge of the clock. The

output data are valid on the rising edge of the

clock for I channel and on the falling edge of the

clock for Q channel. The digital data out from the

different stages must be time delayed depending

on their order of conversion. Then a digital data

correction completes the processing and ensures

the validity of the ending codes on the output bus.

The structure has been specifically designed to

accept differential signals.

The TSA1203 is pin to pin compatible with the

dual 10 bits/20Msps, TSA1005-20, the dual 10bits

/40Msps, TSA1005-40 and the dual 12bits/

20Msps,TSA1204.

COMPLEMENTARY FUNCTIONS

Some functionalities have been added in order to

simplify as much as possible the application

board. These operational modes are described as

followed.

Output Enable (OEB)

When set to low level (VIL), all digital outputs

remain active and are in low impedance state.

When set to high level (VIH), all digital outputs

buffers are in high impedance state while the

converter goes on sampling. When OEB is set to a

low level again, the data are then present on the

output with a very short Ton delay.

Therefore, this allows the chip select of the device.

The timing diagram summarizes this functionality.

In order to remain in the normal operating mode,

this pin should be grounded through a low value of

resistor.

SELECT

The digital data out from each ADC cores are mul-

tiplexed together to share the same output bus.

This prevents from increasing the number of pins

and enables to keep the same package as single

channel ADC like TSA1201.

The selection of the channel information is done

through the "SELECT" pin. When set to high level

(VIH), the I channel data are present on the bus

D0-D11. When set to low level (VIL), the Q chan-

nel data are on the output bus D0-D11.

Connecting SELECT to CLK allows I and Q chan-

nels to be simultaneously present on D0-D11; I

channel on the rising edge of the clock and Q

channel on the falling edge of the clock. (see tim-

ing diagram page 2).

REFERENCES AND COMMON MODE

CONNECTION

VREFM must be always connected externally.

Internal reference and common mode

In the default configuration, the ADC operates with

its own reference and common mode voltages

generated by its internal bandgap. VREFM pins

are connected externally to the Analog Ground

while VREFP (respectively INCM) are set to their

internal voltage of 0.89V (respectively 0.46V). It is

recommended to decouple the VREFP and INCM

in order to minimize low and high frequency noise

(refer to Figure 1).

Figure 1 : Internal reference and common mode

setting

TSA1203

VIN

VINB

VREFM

1.03V

VREFP

330pF

4.7uF

10nF

INCM

330pF

4.7uF

10nF

0.57V

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