| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TDA9106 Datasheet(PDF) 17 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TDA9106 Datasheet(HTML) 17 Page - STMicroelectronics |
|
17 / 30 page ![]() OPERATING DESCRIPTION I - GENERAL CONSIDERATIONS I.1 - Power Supply The typical values of the power supply voltages VCC and VDD are respectively 12V and 5V. Perfect operationis obtained if VCC and VDD are maintened in the limits : 10.8 to 13.2V and 4.5 to 5.5V. In order to avoid erratic operation of the circuit during transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputsof the circuit are inhibited if VCC is less than 7.5V typically. In the same manner,VDD is monitored and internal set-up is made until VDD reaches 4V (see I 2C Control Table for power on reset). In order to have a verygood powersupply rejection, the circuit is internally powered by several internal voltage references (the unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal one. If needed, these voltage references can be used (until load is less than 5mA).Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connectedto ground,in order to minimize the noise and consequently the “jitter” on vertical and hori- zontal output signals. I.2 - I 2C Control TDA9106 belongs to the I 2C controlled device fam- ily, instead of being controlled by DC voltages on dedicated control pins, each adjustment can be realized through the I 2C Interface. The I 2C bus is a serial bus with a clock and a data input. The general function and the bus protocolare specified in the Philips-bus data sheets. The interface (Data and Clock) is TTL-level com- patible. The internal threshold level of the input comparator is 2.2V (when VDD is 5V). Spikes of up to 50ns are filtered by an integrator and maximum clock speed is limited to 400kHz. The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply information (1 byte) to the micro-processor. The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to transmit the IC-address(7 bits-8C) and the read/write bit (0 write - 1 read). I.3 - Write Mode In write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect)and the thirdbyte the correspond- ing data byte.It is possible to send more than one data byte to the IC. If after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data bytes without sending the IC address or subaddress.It can be useful so as to reinitialize the whole controls very quickly (flash manner). This procedure can be finished by a stop condition. The circuit has 16 adjustment capabilities: 3 for Horizontal part, 4 for Vertical one, 2 for E/W correc- tion, 2 for original Corner correction, 2 for the Dynamic Horizontal phase control,1 for Moire op- tion and 2 for Horizontal Dynamic Focus. 20 bits are also dedicated to several controls (ON/OFF, Horizontal Safety Frequency, Synchro Priority, Detection Refresh and Xray reset). I.4 - Read Mode During read mode the second byte transmits the reply information. The reply byte contains Horizontal and Vertical Lock/Unlock status, Xray activated or not, the Hori- zontal and Vertical polarity detection. It also con- tains Synchro detection status that is useful for µP to assign Sync priority. A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and SCL) to high impedance. See I 2C Subaddressand control tables. I.5 - Synchro Processor The internal Sync Processor allows the TDA9106 to accept any kind of input synchro signals : - separated Horizontal & Vertical TTL-compatible sync signals, - composite Horizontal &Vertical TTL-compatible sync signals, - sync on green or composite video signal. TDA9106 17/30 |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |