M38046FFHKP datasheet(90/387 Pages) RENESAS

90 / 387 page

1-72

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

Example of Master Transmission

An example of master transmission in the standard clock mode, at

the SCL frequency of 100 kHz and in the ACK return mode is

shown below.

➀ Set a slave address in the high-order 7 bits of the I2C slave ad-

dress register and “0” into the RWB bit.

➁ Set the ACK return mode and SCL = 100 kHz by setting “8516”

in the I2C clock control register (S2: address 001516).

➂ Set “0016” in the I2C status register (S1: address 001316) so

that transmission/reception mode can become initializing condi-

tion.

➃ Set a communication enable status by setting “0816” in the I2C

control register (S1D: address 001416).

➄ Confirm the bus free condition by the BB flag of the I2C status

➅ Set the address data of the destination of transmission in the

high-order 7 bits of the I2C data shift register (S0: address

001116) and set “0” in the least significant bit.

➆ Set “F016” in the I2C status register (S1: address 001316) to

generate a START condition. At this time, an SCL for 1 byte and

an ACK clock automatically occur.

➇ Set transmit data in the I2C data shift register (S0: address

001116). At this time, an SCL and an ACK clock automatically

occur.

➈ When transmitting control data of more than 1 byte, repeat step

➇.

➉ Set “D016” in the I2C status register (S1: address 001316) to

generate a STOP condition if ACK is not returned from slave re-

ception side or transmission ends.

Example of Slave Reception

An example of slave reception in the high-speed clock mode, at

the SCL frequency of 400 kHz, in the ACK non-return mode and

using the addressing format is shown below.

➀ Set a slave address in the high-order 7 bits of the I2C slave ad-

dress register and “0” in the RWB bit.

➁ Set the no ACK clock mode and SCL = 400 kHz by setting

“2516” in the I2C clock control register (S2: address 001516).

➂ Set “0016” in the I2C status register (S1: address 001316) so

that transmission/reception mode can become initializing condi-

tion.

➃ Set a communication enable status by setting “0816” in the I2C

control register (S1D: address 001416).

➄ When a START condition is received, an address comparison is

performed.

➅ •When all transmitted addresses are “0” (general call):

AD0 of the I2C status register (S1: address 001316) is set to “1”

and an interrupt request signal occurs.

• When the transmitted addresses agree with the address set in

➀:

AAS of the I2C status register (S1: address 001316) is set to

“1” and an interrupt request signal occurs.

• In the cases other than the above AD0 and AAS of the I2C sta-

tus register (S1: address 001316) are set to “0” and no interrupt

request signal occurs.

➆ Set dummy data in the I2C data shift register (S0: address

001116).

➇ When receiving control data of more than 1 byte, repeat step ➆.

➈ When a STOP condition is detected, the communication ends.

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