M38043F8HKP datasheet(16/387 Pages) RENESAS

16 / 387 page

xii

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

Fig. 3.5.31 Structure of UART3 control register ...................................................................... 3-70

Fig. 3.5.32 Structure of AD/DA control register ....................................................................... 3-70

Fig. 3.5.33 Structure of AD conversion register 1 .................................................................. 3-71

Fig. 3.5.34 Structure of DAi conversion register (i = 1, 2) .................................................... 3-71

Fig. 3.5.35 Structure of AD conversion register 2 .................................................................. 3-71

Fig. 3.5.36 Structure of Interrupt source selection register ................................................... 3-72

Fig. 3.5.37 Structure of Interrupt edge selection register ...................................................... 3-73

Fig. 3.5.38 Structure of CPU mode register ............................................................................ 3-73

Fig. 3.5.39 Structure of Interrupt request register 1 ............................................................... 3-74

Fig. 3.5.40 Structure of Interrupt request register 2 ............................................................... 3-74

Fig. 3.5.41 Structure of Interrupt control register 1 ................................................................ 3-75

Fig. 3.5.42 Structure of Interrupt control register 2 ................................................................ 3-75

Fig. 3.5.43 Structure of Flash memory control register 0 ...................................................... 3-76

Fig. 3.5.44 Structure of Flash memory control register 1 ...................................................... 3-77

Fig. 3.5.45 Structure of Flash memory control register 2 ...................................................... 3-77

Fig. 3.5.46 Structure of Port Pi pull-up control register (i = 0 to 2, 4 to 6) ....................... 3-78

Fig. 3.5.47 Structure of Port P3 pull-up control register ........................................................ 3-78

Fig. 3.5.48 Structure of I2C slave address register i (i = 0 to 2) ......................................... 3-79

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