M38042F5HKP datasheet(96/387 Pages) RENESAS

96 / 387 page

1-78

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

WIT instruction

STP instruction

Timing

φ (internal clock)

STP instruction

Main clock stop bit

1/2

1/4

XIN

XOUT

XCOUT

XCIN

Interrupt request

Reset

Interrupt disable flag l

Port XC

switch bit

“1”

“0”

Low-speed

mode

High-speed or

middle-speed

mode

Middle-speed mode

High-speed or

low-speed mode

Main clock division ratio

selection bits (Note 1)

Notes 1: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port Xc switch bit (b4) to “1”.

2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset. The count source before executing the STP

instruction is supplied as the count source at executing STP instruction.

3: When bit 0 of MISRG is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is

“1”, set the appropriate value to them in accordance with oscillation stablizing time required by the using oscillator

because nothing is automatically set into timer 1 and prescaler 12.

4: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.

Main clock division ratio

selection bits (Note 1)

Prescaler 12

Timer 1

Reset or

STP instruction

(Note 2)

Divider

(Note 3)

Reset

(Note 4)

Fig. 75 System clock generating circuit block diagram

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