M38040F5HKP datasheet(15/387 Pages) RENESAS

15 / 387 page

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

Fig. 3.2.14 A/D conversion standard characteristics (f(XIN) = 8 MHz) ................................. 3-23

Fig. 3.2.15 A/D conversion standard characteristics (f(XIN) = 12 MHz) ............................... 3-24

Fig. 3.2.16 A/D conversion standard characteristics (f(XIN) = 16 MHz) ............................... 3-25

Fig. 3.2.17 D/A conversion standard characteristics ............................................................... 3-26

Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-29

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-30

Fig. 3.3.3 Sequence of setting serial I/Oi (i = 1, 3) control register again ......................... 3-33

Fig. 3.3.4 Ceramic resonator circuit .......................................................................................... 3-38

Fig. 3.3.5 Initialization of processor status register ................................................................ 3-40

Fig. 3.3.6 Sequence of PLP instruction execution .................................................................. 3-41

Fig. 3.3.7 Stack memory contents after PHP instruction execution ..................................... 3-41

Fig. 3.3.8 Status flag at decimal calculations .......................................................................... 3-41

_____________

Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-43

Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-44

Fig. 3.4.3 Wiring for CNVSS pin .................................................................................................. 3-44

Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line ........................................ 3-45

Fig. 3.4.5 Analog signal line and a resistor and a capacitor ................................................ 3-46

Fig. 3.4.6 Wiring for a large current signal line ...................................................................... 3-47

Fig. 3.4.7 Wiring of signal lines where potential levels change frequently ......................... 3-47

Fig. 3.4.8 VSS pattern on the underside of an oscillator ........................................................ 3-48

Fig. 3.4.9 Setup for I/O ports ..................................................................................................... 3-48

Fig. 3.4.10 Watchdog timer by software ................................................................................... 3-49

Fig. 3.5.1 Structure of Port Pi .................................................................................................... 3-50

Fig. 3.5.2 Structure of Port Pi direction register ..................................................................... 3-50

Fig. 3.5.3 Structure of Timer 12, X count source selection register .................................... 3-51

Fig. 3.5.4 Structure of Timer Y, Z count source selection register ...................................... 3-52

Fig. 3.5.5 Structure of MISRG ................................................................................................... 3-53

Fig. 3.5.6 Structure of I2C data shift register ........................................................................... 3-53

Fig. 3.5.7 Structure of I2C special mode status register ........................................................ 3-54

Fig. 3.5.8 Structure of I2C status register ................................................................................. 3-55

Fig. 3.5.9 Structure of I2C control register ............................................................................... 3-56

Fig. 3.5.10 Structure of I2C clock control register ................................................................... 3-57

Fig. 3.5.11 Structure of I2C START/STOP condition control register ................................... 3-58

Fig. 3.5.12 Structure of I2C special mode control register ..................................................... 3-58

Fig. 3.5.13 Structure of Transmit/Receive buffer register 1, Transmit/Receive buffer register 3 .... 3-59

Fig. 3.5.14 Structure of Serial I/O1 status register, Serial I/O3 status register ................. 3-59

Fig. 3.5.15 Structure of Serial I/O1 control register ................................................................ 3-60

Fig. 3.5.16 Structure of UART1 control register ...................................................................... 3-61

Fig. 3.5.17 Structure of Baud rate generator i ........................................................................ 3-61

Fig. 3.5.18 Structure of Serial I/O2 control register ................................................................ 3-62

Fig. 3.5.19 Structure of Watchdog timer control register ....................................................... 3-62

Fig. 3.5.20 Structure of Serial I/O2 register ............................................................................. 3-63

Fig. 3.5.21 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-63

Fig. 3.5.22 Structure of Timer 1 ................................................................................................ 3-64

Fig. 3.5.23 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-64

Fig. 3.5.24 Structure of Timer XY mode register .................................................................... 3-65

Fig. 3.5.25 Structure of Timer Z low-order, Timer Z high-order ........................................... 3-66

Fig. 3.5.26 Structure of Timer Z mode register ....................................................................... 3-66

Fig. 3.5.27 Structure of PWM control register ......................................................................... 3-68

Fig. 3.5.28 Structure of PWM prescaler ................................................................................... 3-68

Fig. 3.5.29 Structure of PWM register ...................................................................................... 3-68

Fig. 3.5.30 Structure of Serial I/O3 control register ................................................................ 3-69

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