M38047F1HKP datasheet(13/387 Pages) RENESAS

13 / 387 page

3804 Group (Spec.H)

List of figures

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

Fig. 2.5.11 Structure of Interrupt source selection register ................................................... 2-91

Fig. 2.5.12 Structure of Interrupt request register 1 ............................................................... 2-92

Fig. 2.5.13 Structure of Interrupt request register 2 ............................................................... 2-92

Fig. 2.5.14 Structure of Interrupt control register 1 ................................................................ 2-93

Fig. 2.5.15 Structure of Interrupt control register 2 ................................................................ 2-93

Fig. 2.5.16 I2C-BUS connection structure ................................................................................. 2-94

Fig. 2.5.17 I2C-BUS communication format example .............................................................. 2-95

Fig. 2.5.18 RESTART condition of master reception .............................................................. 2-96

Fig. 2.5.19 SCL waveforms when synchronizing clocks ......................................................... 2-97

Fig. 2.5.20 Initial setting example for SMBUS communication .............................................. 2-99

Fig. 2.5.21 Read Word protocol communication as SMBUS master device ..................... 2-100

Fig. 2.5.22 Generating of START condition and transmission process of slave address + write bit ... 2-101

Fig. 2.5.23 Transmission process of command ..................................................................... 2-102

Fig. 2.5.24 Transmission process of RESTART condition and slave address + read bit ... 2-103

Fig. 2.5.25 Reception process of lower data ......................................................................... 2-104

Fig. 2.5.26 Reception process of upper data ........................................................................ 2-105

Fig. 2.5.27 Generating of STOP condition ............................................................................. 2-106

Fig. 2.5.28 Communication example as SMBUS slave device ............................................ 2-107

Fig. 2.5.29 Reception process of START condition and slave address ............................ 2-108

Fig. 2.5.30 Reception process of command ........................................................................... 2-109

Fig. 2.5.31 Reception process of RESTART condition and slave address ....................... 2-110

Fig. 2.5.32 Transmission process of lower data .................................................................... 2-111

Fig. 2.5.33 Transmission process of upper data ................................................................... 2-112

Fig. 2.5.34 Reception of STOP condition ............................................................................... 2-113

Fig. 2.6.1 Memory map of registers relevant to PWM ......................................................... 2-118

Fig. 2.6.2 Structure of PWM control register ......................................................................... 2-118

Fig. 2.6.3 Structure of PWM prescaler ................................................................................... 2-119

Fig. 2.6.4 Structure of PWM register ...................................................................................... 2-119

Fig. 2.6.5 Connection diagram ................................................................................................. 2-120

Fig. 2.6.6 PWM output timing ................................................................................................... 2-120

Fig. 2.6.7 Setting of relevant registers ................................................................................... 2-121

Fig. 2.6.8 PWM output .............................................................................................................. 2-121

Fig. 2.6.9 Control procedure ..................................................................................................... 2-122

Fig. 2.7.1 Memory map of registers relevant to A/D converter ........................................... 2-123

Fig. 2.7.2 Structure of AD/DA control register ....................................................................... 2-123

Fig. 2.7.3 Structure of AD conversion register 1 .................................................................. 2-124

Fig. 2.7.4 Structure of AD conversion register 2 .................................................................. 2-124

Fig. 2.7.5 Structure of Interrupt source selection register ................................................... 2-125

Fig. 2.7.6 Structure of Interrupt request register 2 ............................................................... 2-126

Fig. 2.7.7 Structure of Interrupt control register 2 ................................................................ 2-126

Fig. 2.7.8 Connection diagram ................................................................................................. 2-127

Fig. 2.7.9 Relevant registers setting ....................................................................................... 2-127

Fig. 2.7.10 Control procedure (10-bit A/D mode) .................................................................. 2-128

Fig. 2.7.11 Connection diagram ............................................................................................... 2-129

Fig. 2.7.12 Relevant registers setting ..................................................................................... 2-129

Fig. 2.7.13 Control procedure (8-bit A/D mode) .................................................................... 2-130

Fig. 2.8.1 Memory map of registers relevant to D/A converter ........................................... 2-132

Fig. 2.8.2 Structure of Port P5 direction register .................................................................. 2-133

Fig. 2.8.3 Structure of AD/DA control register ....................................................................... 2-133

Fig. 2.8.4 Structure of DAi converter register ........................................................................ 2-134

Fig. 2.8.5 Peripheral circuit example ....................................................................................... 2-135

Fig. 2.8.6 Speaker output example ......................................................................................... 2-135

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