M38041F0HKP datasheet(77/387 Pages) RENESAS

77 / 387 page

1-59

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

XIN

Data bus

XCIN

“10”

“00”

“01”

Main clock division

ratio selection bits

(Note)

“0”

“1”

1/16

Watchdog timer H count

source selection bit

Reset

circuit

STP instruction disable bit

Watchdog timer H (8)

“FF16” is set when

watchdog timer

control register is

written to.

Internal reset

RESET

Watchdog timer L (8)

Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

STP instruction

“FF16” is set when

watchdog timer

control register is

written to.

Reset release time waiting

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software run-away). The watchdog timer consists of an

8-bit watchdog timer L and an 8-bit watchdog timer H.

Watchdog Timer Initial Value

Watchdog timer L is set to “FF16” and watchdog timer H is set to

“FF16” by writing to the watchdog timer control register (address

001E16) or at a reset. Any write instruction that causes a write sig-

nal can be used, such as the STA, LDM, CLB, etc. Data can only

be written to bits 6 and 7 of the watchdog timer control register.

Regardless of the value written to bits 0 to 5, the above-mentioned

value will be set to each timer.

Watchdog Timer Operations

The watchdog timer stops at reset and a countdown is started by

the writing to the watchdog timer control register. An internal reset

occurs when watchdog timer H underflows. The reset is released

after its release time. After the release, the program is restarted

from the reset vector address. Usually, write to the watchdog timer

control register by software before an underflow of the watchdog

timer H. The watchdog timer does not function if the watchdog

timer control register is not written to at least once.

Fig. 55 Structure of Watchdog timer control register

When bit 6 of the watchdog timer control register is kept at “0”, the

STP instruction is enabled. When that is executed, both the clock

and the watchdog timer stop. Count re-starts at the same time as

the release of stop mode (Note). The watchdog timer does not

stop while a WIT instruction is executed. In addition, the STP in-

struction is disabled by writing “1” to this bit again. When the STP

instruction is executed at this time, it is processed as an undefined

instruction, and an internal reset occurs. Once a “1” is written to

this bit, it cannot be programmed to “0” again.

The following shows the period between the write execution to the

watchdog timer control register and the underflow of watchdog

timer H.

Bit 7 of the watchdog timer control register is “0”:

when XCIN = 32.768 kHz; 32 s

when XIN = 16 MHz; 65.536 ms

Bit 7 of the watchdog timer control register is “1”:

when XCIN = 32.768 kHz; 125 ms

when XIN = 16 MHz; 256

µs

Note: The watchdog timer continues to count even while waiting for a stop

release. Therefore, make sure that watchdog timer H does not un-

derflow during this period.

Fig. 54 Block diagram of Watchdog timer

Watchdog timer H (for read-out of high-order 6 bit)

STP instruction disable bit

0: STP instruction enabled

1: STP instruction disabled

Watchdog timer H count source selection bit

0: Watchdog timer L underflow

1: f(XIN)/16 or f(XCIN)/16

Watchdog timer control register

(WDTCON : address 001E16)

M38041F0HKP Datasheet(PDF) 77 Page - Renesas Technology Corp

M38041F0HKP Datasheet(HTML) 77 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL