SH7708 datasheet(198/633 Pages) RENESAS

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180

Bit 2: CKS2

Bit 1: CKS1

Bit 0: CKS0

Clock Division Ratio

Overflow Period

(when P

φ = 15 MHz)

0001

(Initial value)

µs

1/4

µs

1/16

273

µs

1/32

546

µs

1/64

1.09 ms

1/256

4.36 ms

1/1024

17.46 ms

1/4096

69.84 ms

Note:

If bits CKS2–CKS0 are modified when the WDT is running, the up-count may not be

performed correctly. Ensure that these bits are modified only when the WDT is not running.

9.9.3

Notes on Register Access

The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are

more difficult to write to than other registers. The procedure for writing to these registers are given

below.

Writing to WTCNT and WTCSR: These registers must be written by a word transfer

instruction. They cannot be written by a byte or longword transfer instruction. When writing to

WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in

figure 9.5. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the

write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.

H'5A

Write data

Address: H'FFFFFE84

WTCNT write

H'A5

Write data

Address: H'FFFFFE86

WTCSR write

Figure 9.5 Writing to WTCNT and WTCSR

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