SH7708 datasheet(196/633 Pages) RENESAS

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9.9

WDT Registers

9.9.1

Watchdog Timer Counter (WTCNT)

The watchdog timer counter (WTCNT) is an 8-bit read/write counter that increments on the

selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an

interrupt in interval time mode. Its address is H'FFFFFF84. The WTCNT counter is initialized to

H'00 only by a power-on reset through the RESET pin. Use a word access to write to the WTCNT

counter, with H'5A in the upper byte. Use a byte access to read WTCNT.

Bit:

Initial value:

R/W:

R/W

9.9.2

Watchdog Timer Control/Status Register (WTCSR)

The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of

bits to select the clock used for the count, bits to select the timer mode, and overflow flags. Its

address is H'FFFFFF86. The WTCSR register is initialized to H'00 only by a power-on reset

through the RESET pin. When a WDT overflow causes an internal reset, the WTCSR retains its

value. When used to count the clock settling time for canceling a standby, it retains its value after

counter overflow. Use a word access to write to the WTCSR counter, with H'A5 in the upper byte.

Use a byte access to read WTCSR.

Bit:

TME

WT/

RSTS

WOVF

IOVF

CKS2

CKS1

CKS0

Initial value:

R/W:

R/W

Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the

WDT in standby mode or when changing the clock frequency.

Bit 7: TME

Description

Timer disabled: Count-up stops and WTCNT value is retained

(Initial value)

Timer enabled

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