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SH7708 Datasheet(PDF) 191 Page - Renesas Technology Corp

No. de pieza SH7708
Descripción Electrónicos  SuperH??RISC engine
PDF  633 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7708 Datasheet(HTML) 191 Page - Renesas Technology Corp

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Bit 14: IFC2
Bit 2: IFC1
Bit 1: IFC0
Description
000
× 1
(Initial value)
001
× 1/2
100
× 1/3
110
× 1/4
Note:
Do not set the interunal clock frequency lower then the CKIO frequency.
Bits 13, 1 and 0—Peripheral Clock Frequency Division Ratio (PFC): These bits specify the
division ratio of the peripheral clock frequency with respect to the frequency of the output
frequency of PLL circuit 1 or the frequency of the CKIO pin.
Bit 13: PFC2
Bit 1: PFC1
Bit 0: PFC0
Description
000
× 1
001
× 1/2
100
× 1/3
110
× 1/4
Note:
Do not set the peripheral clock frequency higher then the frequency of the CKIO pin.
Bit 8—Clock Enable (CKOEN): Used to output a clock in operating mode 3–6 from the CKIO pin
or to fix the level of the CKIO pin in clock operation modes 3 and 4. Even when the level is fixed,
the SH7708R will operate internally at the frequency before the level was fixed. In case of clock
operating mode 0–2, set this bit to 1. In case of clock operating mode 7, the CKIO pin becomes an
input pin irrespective of the value of this bit.
Bit 8: CKOEN
Description
0
Fixes the level of CKIO terminal.
1
Outputs a clock from the CKIO pin.
(Initial value)
Bit 7—PLL Circuit Enable (PLLEN): Specifies the on/off state of PLL circuit 1. This bit is valid
in clock operating modes 3 and 4. PLL circuit 1 goes on when the clock operating mode is 0–2 or
7 irrespective of the value of PLLEN.
Bit 7: PLLEN
Description
0
PLL circuit 1 is not used.
(Initial value)
1
PLL circuit 1 is used.
Bit 6—PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1
will be in standby mode at the frequency specified by the STC bit. This function is valid in clock
operating modes 3 and 4.



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