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SH7708 Datasheet(PDF) 482 Page - Renesas Technology Corp |
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SH7708 Datasheet(HTML) 482 Page - Renesas Technology Corp |
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482 / 633 page ![]() 464 CKIO RD/ WR D31–D0 (read) D31–D0 (write) RAS CASxx BS CS2 or CS3 A25–A16 A15–A0 Tr tAD Row address Column address Column address tAD tAD tRWD tWDH3 tRDS2 tRDS2 tWDS tRDH2 tWDH3 tCSD1 tBSD tBSD tCSD1 tAS tAS tAH tAH tAH tRWH tAD tAD Tc2 (Tpc) tWDH1 tWDD2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 tRWD tRASD1 tCASD1 tCASD1 tCASD1 tCASD1 Row address tRASD2 tRDH2 tWDD2 Column address Column address Row address Figure 16.29 DRAM Burst Bus Cycle (EDO Mode, RCD = 0, AnW = 1, TPC = 0) |
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