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SH7708 Datasheet(PDF) 480 Page - Renesas Technology Corp |
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SH7708 Datasheet(HTML) 480 Page - Renesas Technology Corp |
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480 / 633 page ![]() 462 CKIO RD/ WR D31–D0 (read) D31–D0 (write) RAS CASxx BS CS2 or CS3 A25–A16 Tr Tc1 Tc2 (Tpc) tAD tAD tAS tAD tRASD1 tAD tAS tAH tRWD tAH A15–A0 tRWH tRWD tRASD2 tCASD1 tCASD1 tWDH3 tWDH1 tRDH2 tRDS2 tWDD2 tBSD tBSD tCSD1 tCSD1 tWDS Row address Row address Column address Figure 16.27 DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 1, TPC = 0) |
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