H8SXSLASH1663M datasheet(71/1504 Pages) RENESAS

No. de pieza	H8SX/1663M

Descripción Electrónicos	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

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Fabricante Electrónico	RENESAS [Renesas Technology Corp]

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Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 39 of 1468

REJ09B0412-0200

• Stack Structure

The stack structure of PC at a subroutine branch and that of PC and CCR at an exception

handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.

(a) Subroutine Branch

(b) Exception Handling

(24 bits)

EXR*1

Reserved*1, *3

CCR

(24 bits)

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored on return.

(SP

)

Reserved

Figure 2.5 Stack Structure (Middle and Advanced Modes)

2.2.4

Maximum Mode

The program area is extended to 4 Gbytes as compared with that in advanced mode.

• Address Space

The maximum address space of 4 Gbytes can be linearly accessed.

• Extended Registers (En)

The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit

segments of 32-bit registers or address registers.

• Instruction Set

All instructions and addressing modes can be used.

• Exception Vector Table and Memory Indirect Branch Addresses

In maximum mode, the top area starting at H'00000000 is allocated to the exception vector

table. One branch address is stored per 32 bits. The structure of the exception vector table is

shown in figure 2.6.

H8SX/1663M Datasheet(PDF) 71 Page - Renesas Technology Corp