H8SXSLASH1663M datasheet(505/1504 Pages) RENESAS

505 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 473 of 1468

REJ09B0412-0200

11.3.7

EXDMA Address Control Register (EDACR)

EDACR sets the operating modes and transfer methods.

AMS

R/W

DIRS

R/W



ARS0

R/W

RPTIE

R/W

ARS1

R/W

Bit

Bit Name

Initial Value

R/W



SAT1

R/W

SAT0

R/W



DAT0

R/W



DAT1

R/W

Bit

Bit Name

Initial Value

R/W

SARIE

R/W



SARA4

R/W

SARA3

R/W

SARA0

R/W

SARA2

R/W

SARA1

R/W

Bit

Bit Name

Initial Value

R/W

DARIE

R/W



DARA4

R/W

DARA3

R/W

DARA0

R/W

DARA2

R/W

DARA1

R/W

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial

value

R/W

Description

AMS

R/W

Address Mode Select

Selects single address mode or dual address mode.

When single address mode is selected,

EDACK pin is

valid due to the EDACKE bit setting in EDMDR.

0: Dual address mode

1: Single address mode

DIRS

R/W

Single Address Direction Select

Specifies the data transfer direction in single address

mode. In dual address mode, the specification by this

bit is ignored.

In cluster transfer mode, the internal cluster buffer will

be the source or destination in place of the external

device with

DACK.

0: EDSAR transferred as a source address

1: EDDAR transferred as a destination address

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